[Libre-soc-dev] new svp64 page

[Luke Kenneth Casson Leighton]

On Thu, Dec 10, 2020 at 3:36 AM Jacob Lifshay <programmerjake at gmail.com>
wrote:

> Couldn't we just use the already existing VSX instructions for some of
> that and just SV-ify them,


on the basis that when in the v3.1B Prefix, by using the 16 EXT01 SV-P64
identifiers we've *already* got a "mode" that can easily identify the VSX
instructions opcodes.  i.e. we *can* cleanly use the entirety of the VSX
opcode space.  sorry that was a lot of words.  when we set the EXT01 prefix
bits 6:11 to indicate "SVP64".


where the SV prefix just takes the base
> operation:
> using a SV-prefixed form of vaddshs would act as if the vaddshs was
> just a scalar signed 16-bit saturating add, adding SV-style
> vectorization if the src/dest registers are set as vectors.
> using a SV-prefixed form of vavguw would act as if the vavguw was just
> a scalar unsigned 16-bit average operation.
>
> Using those (and other similar instructions) would make it waay easier
> to get the operations we need with less friction, since the encodings
> already exist.
>

they do... which makes for a compelling argument, vs "time spent
reinventing them".  the concern that i have about that idea is two-fold:
firstly, it sends a message to the world's largest software company (IBM)
that DSP/SIMD-style 12-15 year old ISAs are still acceptable today.
secondly, when it comes to ISA review we have to spend considerable time
explaining which *parts* of the SIMD ISA were "extracted" (and why) - as
opposed to simply saying, "lessons from the past teach us that it's time
for a clean slate".  at which point, there's no need to refer to the old
SIMD ISA except in passing.

i think part of the answer comes from a comparison.  here's what a modern
(actual) Vector ISA looks like when it's had input from companies such as
AndesSTAR, the world's leading supplier of Audio DSPs, with consultation
from some of the world's leading experts with over 40 years experience each
in historical Vector ISAs (Cray and more):

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-fixed-point-arithmetic-instructions

they provide:

* one sat-add,
* one sat-sub,
* one avg-add
* one avg-sub
* one sat/round mul
* one scaling-shift with clip (signed and unsigned)
* one narrowing with clip (signed and unsigned)

in addition, section 12.9, mix/max is also provided (signed and unsigned).

below is a table of a *SMALL* fraction of what a 12-15 year old DSP/SIMD
style ISA looks like, that was designed behind closed doors, without
external consultation, at a time when SIMD, across the industry, was being
pushed as a way to boost performance.

ARC, AndesSTAR and Texas Instruments DSP ISAs all look just as awful:
they're all SIMD ISAs, just like VSX.

l.

vsum4ubs v2.03 Vector Sum across Quarter Unsigned Byte Saturate
vsum4shs v2.03 Vector Sum across Quarter Signed Halfword Saturate
vsum2sws v2.03 Vector Sum across Half Signed Word Saturate
vsum4sbs v2.03 Vector Sum across Quarter Signed Byte Saturate
vsumsws  v2.03 Vector Sum across Signed Word Saturate

vaddubm v2.03 Vector Add Unsigned Byte Modulo
vadduhm v2.03 Vector Add Unsigned Halfword Modulo
vadduwm v2.03 Vector Add Unsigned Word Modulo
vaddudm v2.07 Vector Add Unsigned Doubleword Modulo
vadduqm v2.07 Vector Add Unsigned Quadword Modulo
vaddcuq v2.07 Vector Add & write Carry Unsigned Quadword
vaddcuw v2.03 Vector Add & Write Carry-Out Unsigned Word
vaddubs v2.03 Vector Add Unsigned Byte Saturate
vadduhs v2.03 Vector Add Unsigned Halfword Saturate
vadduws v2.03 Vector Add Unsigned Word Saturate
vaddsbs v2.03 Vector Add Signed Byte Saturate
vaddshs v2.03 Vector Add Signed Halfword Saturate
vaddsws v2.03 Vector Add Signed Word Saturate
vsububm v2.03 Vector Subtract Unsigned Byte Modulo
vsubuhm v2.03 Vector Subtract Unsigned Halfword Modulo
vsubuwm v2.03 Vector Subtract Unsigned Word Modulo
vsubudm v2.07 Vector Subtract Unsigned Doubleword Modulo
vsubuqm v2.07 Vector Subtract Unsigned Quadword Modulo
vsubcuq v2.07 Vector Subtract & write Carry Unsigned Quadword
vsubcuw v2.03 Vector Subtract & Write Carry-Out Unsigned Word
vsububs v2.03 Vector Subtract Unsigned Byte Saturate
vsubuhs v2.03 Vector Subtract Unsigned Halfword Saturate
vsubuws v2.03 Vector Subtract Unsigned Word Saturate
vsubsbs v2.03 Vector Subtract Signed Byte Saturate
vsubshs v2.03 Vector Subtract Signed Halfword Saturate
vsubsws v2.03 Vector Subtract Signed Word Saturate

vmaxub v2.03 Vector Maximum Unsigned Byte
vmaxuh v2.03 Vector Maximum Unsigned Halfword
vmaxuw v2.03 Vector Maximum Unsigned Word
vmaxud v2.07 Vector Maximum Unsigned Doubleword
vmaxsb v2.03 Vector Maximum Signed Byte
vmaxsh v2.03 Vector Maximum Signed Halfword
vmaxsw v2.03 Vector Maximum Signed Word
vmaxsd v2.07 Vector Maximum Signed Doubleword
vminub v2.03 Vector Minimum Unsigned Byte
vminuh v2.03 Vector Minimum Unsigned Halfword
vminuw v2.03 Vector Minimum Unsigned Word
vminud v2.07 Vector Minimum Unsigned Doubleword
vminsb v2.03 Vector Minimum Signed Byte
vminsh v2.03 Vector Minimum Signed Halfword
vminsw v2.03 Vector Minimum Signed Word
vminsd v2.07 Vector Minimum Signed Doubleword
vavgub v2.03 Vector Average Unsigned Byte
vavguh v2.03 Vector Average Unsigned Halfword
vavguw v2.03 Vector Average Unsigned Word
vavgsb v2.03 Vector Average Signed Byte
vavgsh v2.03 Vector Average Signed Halfword
vavgsw v2.03 Vector Average Signed Word

vabsdub v3.0 Vector Absolute Difference Unsigned Byte
vabsduh v3.0 Vector Absolute Difference Unsigned Halfword
vabsduw v3.0 Vector Absolute Difference Unsigned Word

vmuloub v2.03 Vector Multiply Odd Unsigned Byte
vmulouh v2.03 Vector Multiply Odd Unsigned Halfword
vmulouw v2.07 Vector Multiply Odd Unsigned Word
vmulosb v2.03 Vector Multiply Odd Signed Byte
vmulosh v2.03 Vector Multiply Odd Signed Halfword
vmulosw v2.07 Vector Multiply Odd Signed Word
vmuleub v2.03 Vector Multiply Even Unsigned Byte
vmuleuh v2.03 Vector Multiply Even Unsigned Halfword
vmuleuw v2.07 Vector Multiply Even Unsigned Word
vmulesb v2.03 Vector Multiply Even Signed Byte
vmulesh v2.03 Vector Multiply Even Signed Halfword
vmulesw v2.07 Vector Multiply Even Signed Word

vmhaddshs  v2.03 Vector Multiply-High-Add Signed Halfword Saturate
vmhraddshs v2.03 Vector Multiply-High-Round-Add Signed Halfword Saturate
vmladduhm  v2.03 Vector Multiply-Low-Add Unsigned Halfword Modulo
vmsumudm   v3.0B Vector Multiply-Sum Unsigned Doubleword Modulo
vmsumubm   v2.03 Vector Multiply-Sum Unsigned Byte Modulo
vmsummbm   v2.03 Vector Multiply-Sum Mixed Byte Modulo
vmsumuhm   v2.03 Vector Multiply-Sum Unsigned Halfword Modulo
vmsumuhs   v2.03 Vector Multiply-Sum Unsigned Halfword Saturate
vmsumshm   v2.03 Vector Multiply-Sum Signed Halfword Modulo
vmsumshs   v2.03 Vector Multiply-Sum Signed Halfword Saturate

vaddeuqm v2.07 Vector Add Extended Unsigned Quadword Modulo
vaddecuq v2.07 Vector Add Extended & write Carry Unsigned Quadword
vsubeuqm v2.07 Vector Subtract Extended Unsigned Quadword Modulo
vsubecuq v2.07 Vector Subtract Extended & write Carry Unsigned Quadword