[Libre-soc-bugs] [Bug 1044] SVP64 implementation of pow(x,y,z)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1044

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=22e9003

jacob what i'm doing here is a mini-code-morphed-demo investigating
the viability of using bigmul REMAP. i did the exact same thing with
test_caller_svp64_chacha20.py, am helping sadoon on bug #1157 / bug #1159
and ed25519 will need the same thing: looking for the patterns and
condensing them down so that bigmul REMAP (preferably without needing
Vertical-First) can just go *BLAM*, one instruction, the whole lot.

i don't think it's going to be possible to do without Vertical-First
but one "trick" of Vertical-First is that there is "end of inner loop"
notification when using "svstep."

by checking the *correct bit* of CR0 you can do branch-conditional
code that, say, performs that "extra add-with-carry"
this will be quite fascinating to see if that trick works.

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