[Libre-soc-bugs] [Bug 1157] Implement poly1305

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1157

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/irclog/%23libre-soc.2023-09-15.log.html#t2023-09-15T17:39:01

what is happening here is explained in this page
https://libre-soc.org/openpower/sv/biginteger/analysis/

adde uses XER.CA as carry-in and creates XER.CA as carry-out.  therefore
if you do adde adde adde adde with successive register numbers you have
created a big-int add by chaining the carrys together on each adde.
*therefore* you can *replace the adde sequence with **ONE** sv.adde
instruction.

real simple.

the maddedu instruction works similarly by treating one of the
reg pair as a *64-bit* carry-in carry-out.

btw one absolutely critical thing to understand about Simple-V is
that the Vector Length is in **ELEMENTS NOT BITS**. this makes it
natural for humans to work with.

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