[Libre-soc-bugs] [Bug 982] Support PowerPC ABI in ISACaller

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=982

--- Comment #18 from Andrey Miroshnikov <andrey at technepisteme.xyz> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
>
> https://wiki.debian.org/QemuUserEmulation
> 
> very useful.

Thanks, I was able to assemble and run the example (using qemu).


Found another hello world assembler example (which actually explained what
@highest, @higher, @h, @l meant):
https://gist.github.com/sandip4n/09b50786e88968faaecdf42360c85b1b
(otherwise the assembler is exactly the same)

I created a basic unit test which only calls the system call 'sc' instruction
(with reg's preloaded).
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=1be8996cbea4d5bcb96ed9a91c2f0dbfcacf7ee1
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=2c075be04e5603ffb161002a99e4684b41973829

I entered the expected values as per sc instruction definition in PowerISA
v3.1b, Book III, Chapter 4, section 4.3.1 System Linkage Instructions:
SRR0 <- i_ea CIA + 4
SRR1_33:36 42:47 <- 0
SRR1_0:32 37:41 48:63 <- MSR_0:32 37:41 48:63
MSR <- new_value (see below)
NIA <- 0x0000_0000_0000_0C00

The MSR value is defined in Section 7.5 (same book), figure 69.
NIA comes from figure 70.

The Libre-SOC pseudo-code looks similar:
SRR0 <-iea CIA + 4
SRR1[33:36] <- 0
SRR1[42:47] <- 0
SRR1[0:32]  <- MSR[0:32]
SRR1[37:41] <- MSR[37:41]
SRR1[48:63] <- MSR[48:63]
MSR <- new_value
NIA <- 0x0000_0000_0000_0C00


Running the test_caller_syscall.py causes the following assertions to fail
(need to set e.pc to value given by simulator to get other assertion errors):

AssertionError: 0x0 != 0x8: SPR.SRR0 mismatch (sim != expected) 'sc'
My understanding (based on pseudo-code from PowerISA spec and Libre-SOC page),
is that SRR0 will be equal to CIA+4.
At the start of the program I defined cia (pc) as 4, so 8 should be the
expected value. Is the simulator not setting SRR0 at all?

AssertionError: 0x9000000000082903 != 0x9000000000002903: SPR.SRR1 mismatch
(sim != expected) 'sc'
SRR1 is equal to the MSR before the syscall is made, in this case default value
of 0x9000000000002903 was used. Seems like bit 19 is set (where that 8 is).

AssertionError: 1792 != 3072 : pc mismatch (sim != expected) 'sc'
I picked 3072 (0xC00) as I wasn't sure what it's going to be.
However it doesn't make sense where 1792 (0x700) comes from.

Not sure how to proceed (other than digging through the internals of
ISACaller). Am I making an endian-ness error?

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