[Libre-soc-bugs] [Bug 979] Implement C-based Power ISA decoder compiler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=979

--- Comment #59 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Hi folks, I've created a test which can be as a foundation to check the
generated code. The idea is to provide standalone micro-disassembler, which
just fetches the instructions from stdin and prints the very basic disassembly
(instruction name, operands values, operands flags). The Python test builds the
instructions from plain text via insndb, then feeds them to micro-disassembler,
then checks whether the expected output matches the actual one.

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=77fc07a0cb5819a908da042d7a980b44ca782d74

Currently I've checked three variants of addpcis (these have split fields and
signed operands), and svshape vs svshape2 (because these have non-zero operands
and complicated opcode mapping).

Luke, please check whether these are sufficient to mark the task as completed.

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