[Libre-soc-bugs] [Bug 1154] New: Autogeneration of binutils source code for the SVP64 assembler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1154

            Bug ID: 1154
           Summary: Autogeneration of binutils source code for the SVP64
                    assembler
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: ghostmansd at gmail.com
          Reporter: andrey at technepisteme.xyz
                CC: libre-soc-bugs at lists.libre-soc.org
        Depends on: 979
            Blocks: 984
   NLnet milestone: NLnet.2021-08-071.cavatools
 total budget (EUR) 2500
  for completion of
       task and all
          subtasks:
   budget (EUR) for 2500
         this task,
          excluding
  subtasks' budget:
    parent task for 984
 budget allocation:

To reduce the time and effort required to align the binutils assembler with
isndb(?) (whenever changes are made to the Libre-SOC ISA), a code generator
needs to be written. At present, the binutils source has to be modified
manually, which is error-prone and time/effort intensive.

This task will aid with cavatools, as an SVP64 assembler will be required
regardless of the simulator being used (or even hardware), and reduce the
burden on developers picking up future tasks.

See bug #979 comment #55 (https://bugs.libre-soc.org/show_bug.cgi?id=979#c55)
where this task had been suggested.


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=979
[Bug 979] Implement C-based Power ISA decoder compiler
https://bugs.libre-soc.org/show_bug.cgi?id=984
[Bug 984] Support SVP64 in cavatools
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