[Libre-soc-bugs] [Bug 1220] New: An introduction to Formal Verification of Digital Circuits

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1220

            Bug ID: 1220
           Summary: An introduction to Formal Verification of Digital
                    Circuits
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
               URL: https://pretalx.fosdem.org/fosdem-2024/talk/review/ERC
                    K9HTW89NXBA7SFGF8BLMWCTFEZWBG
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Conferences
          Assignee: cestrauss at gmail.com
          Reporter: cestrauss at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

The idea is to give a little background on how Formal Verification work, the
available ecosystem of tools, show some small examples on how to use them, and
some practical results from real-life usage.

-- 
You are receiving this mail because:
You are on the CC list for the bug.