[Libre-soc-bugs] [Bug 980] Implement C-based Power ISA pseudocode compiler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=980

--- Comment #6 from Dmitry Selyutin <ghostmansd at gmail.com> ---
Hi guys! Andrey, I'm sorry, I've missed your message.

(In reply to Andrey Miroshnikov from comment #4)
(In reply to Luke Kenneth Casson Leighton from comment #5)
> (In reply to Andrey Miroshnikov from comment #4)
> > Dmitry, is this task doable?
> 
> yes.
> 
> > Again apologies, I don't remember if we agreed this task is actually
> > possible within the time constraints. 
> 
> it is.
> 
> > My chart on the discussion page
> > proposed to cancel this task.
> 
> no.

Luke, I agree with you it's both doable and can be kept, but we have to
establish the criteria, otherwise we'll put it under risk. We'd better be damn
careful! Here's what I suggest:

1. Stick to developing the key concepts for code generation. Likely only
vanilla PPC at this stage.
2. Generating something to be reused as yet another library; this allows us to
combine it with libopid. I'm thinking of generating a table of per-instruction
callbacks along with their bodies and some context around, like this:

/*
 * Intended to be called from the decoder.
 * Prefix is NOP for vanilla PPC.
 * Just a quick approximation, something more complex is needed.
 */
static void
opsim_add(struct opsim_ctx *ctx,
        uint64_t prefix, uint64_t suffix) {
    /* can be optimized later, don't care for now */
    uint64_t RT = opsim_reg_fetch(ctx, opsim_add_RT(suffix));
    uint64_t RA = opsim_reg_fetch(ctx, opsim_add_RA(suffix));
    uint64_t RB = opsim_reg_fetch(ctx, opsim_add_RB(suffix));

    RT = (RA + RB);

    opsim_reg_store(ctx, opsim_add_RT(suffix), RT);
}

or even:

static void
opsim_add(struct opsim_ctx *ctx,
        uint64_t prefix, uint64_t suffix) {
    /* can be optimized later, don't care for now */
    uint64_t RT = opsim_reg_fetch(ctx, opsim_add_RT(suffix));
    uint64_t RA = opsim_reg_fetch(ctx, opsim_add_RA(suffix));
    uint64_t RB = opsim_reg_fetch(ctx, opsim_add_RB(suffix));

    RT = (RA + RB);

    opsim_reg_store(ctx, opsim_add_RT(suffix),
        (opsim_reg_fetch(ctx, opsim_add_RA(suffix)) +
         opsim_reg_fetch(ctx, opsim_add_RB(suffix)))
    );
}

3. Nothing to be touched yet in the existing codegen, we'll just add C
generation mode into the current generator, due to time constraints. Yes
there's a room for improvement, some things might be done differently. But for
now -- no changes unless lack of them stops us. We'll be under a huge risk
otherwise.

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