[Libre-soc-bugs] [Bug 1213] New: My FOSDEM 2024 talk:

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1213

            Bug ID: 1213
           Summary: My FOSDEM 2024 talk:
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Other
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Conferences
          Assignee: lkcl at lkcl.net
          Reporter: libre-soc at platen-software.de
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

I drafted my first proposal for a talk at FOSDEM:

The Libre-SOC project has been prototyped using an Lattic ECP5 FPGA before
its first [tapeout](https://libre-soc.org/180nm_Oct2020). 
Since then many things have changed. One big change is the use of a different
controller for DDR3 controller called
[gram](https://git.libre-soc.org/?p=gram.git).
To get DDR3 working on the OrangeCrab many changes are needed.

This talk will provide an overview on my work on libre-soc in the past two
years,
an overview of DDR SDRAM interfaces and the PHYs commonly found on FPGAs and
some
ways to debug the OrangeCrab using a
(BeagleWire)[https://www.crowdsupply.com/qwerty-embedded-design/beaglewire]

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