[Libre-soc-bugs] [Bug 1210] sv.bc branching to incorrect address in Vertical-First mode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1210

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/openpower/isa/branch/

if AA then NIA  <-iea EXTS(LI || 0b00)
else       NIA  <-iea CIA + EXTS(LI || 0b00)
if LK then LR <-iea  CIA + 4

(In reply to Andrey Miroshnikov from comment #0)
> While experimenting with sv.bc in Vertical-First, I discovered an issue
> where a branch is not take (although the condition for the branch is met).
> 
> Example test case created in a branch:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=5a174ba4c2d7c19733167933eee71a2761e38695
> 
> Code (With PC/NIA):
> 00 "setvl 0, 0, %d, 1, 1, 1" % maxvl, # VL = MAXVL = 2, vf=1
> 04 "sv.cmpi *cr0, 1, *10, 0x10", # compare reg val with immediate
> 0c "sv.bc 0, *2, 0x10", # jmp if CTR!=0 AND reg  not equal to imm
> 14 "svstep. 27, 1, 0",

this will occur if the jump does NOT take place because the
conditions (CTR!=0 AND reg not eq immed) are not met.

you can check if the conditions are or are not met by adding
*another* nop and increasing the jump from 0x10 to 0x14.

if the address jumped to is 0x18 then your hypothesis is correct.

if the address of the next ecexuted instruction is still 0x14
then the branch is *not taking place* and the simulator is
simply moving to the next instruction.

>   BUT instead NIA is set to 0x14 (svstep., the next insn)

probably because the conditions for *conditional* branching are not met.

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