[Libre-soc-bugs] [Bug 1177] revert unauthorized change to pseudocode language

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1177

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #22)
> (edit: please continue conversation on sc on bug #1207)
> 
> (In reply to Luke Kenneth Casson Leighton from comment #21)
> > (In reply to Jacob Lifshay from comment #20)
> > > I also fixed sc and the previously-working tests for it, since SRR1 is
> > > specified to have bits 33:36 set to 0, 42:43 set to LEV (always 0 for now),
> > > and 44:47 set to 0. SRR1[TRAP] is *not* set.
> > 
> > please revert aaaalll of them. we are compatible with MICROWATT.
> > i keep having to tell you this.
> 
> well, my changes make us *compatible* with microwatt again:

okaay,interesting. can you check that they don't set the LEV bit,
in OP_SC? implementing Hypervisor is completely off-limits.

> on sc-test branch (based off latest master):
> https://git.libre-soc.org/?p=microwatt.git;a=commitdiff;
> h=44eab364aee1a7cb6198cb148d68a065715a434a

oh! good idea. niice teeest :)

> make -C sc_test
> ln -sf sc_test/hello_world.bin main_ram.bin
> make DOCKER=1
> ./core_tb > /dev/null
> 
> gives the following output on my computer:
> before sc:
> SRR0 = 0x0000000012345678 SRR1 = 0x0000000000005678 MSR = 0x90000000783F2903
> sc
> after sc:
> SRR0 = 0x000000000000112C SRR1 = 0x8000000000002903 MSR = 0x80000000783F0001
> before sc:
> SRR0 = 0x0000000012345678 SRR1 = 0x0000000000005678 MSR = 0x9000000000000003
> sc
> after sc:
> SRR0 = 0x000000000000112C SRR1 = 0x8000000000000003 MSR = 0x8000000000000001
> <snip>
> 
> as you can see, microwatt sc doesn't set SRR1[TRAP] (which would be
> 0x20000), and it also clears all the SRR1 bits that sc is supposed to
> (basically SRR1 &= ~0x783f0000)

ok let's track the source... execute1.vhdl

1055             when OP_SC =>
1056                 -- check bit 1 of the instruction is 1 so we know this is
sc;
1057                 -- 0 would mean scv, so generate an illegal instruction
interrupt
1058                 if e_in.insn(1) = '1' then
1059                     v.trap := '1';
1060                     v.advance_nia := '1';
1061                     v.e.intr_vec := 16#C00#;
1062                     if e_in.valid = '1' then
1063                         report "sc";
1064                     end if;
1065                 else
1066                     illegal := '1';
1067                 end if;

so trap=1, intrvec=0xc00...

ahh but for OP_TRAP

1093             when OP_CMP =>
1094             when OP_TRAP =>
1095                 -- trap instructions (tw, twi, td, tdi)
1096                 v.e.intr_vec := 16#700#;
1097                 -- set bit 46 to say trap occurred
1098                 v.e.srr1(47 - 46) := '1';

YYEP,nice catch jacob,sorry for freaking out. yes use a "None" option but
make sure it is documented. i must have missed that when doing the original
HDL/test

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