[Libre-soc-bugs] [Bug 972] addme/subfme carry/overflow is incorrect
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Thu Mar 30 09:04:20 BST 2023
https://bugs.libre-soc.org/show_bug.cgi?id=972
Jacob Lifshay <programmerjake at gmail.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|IN_PROGRESS |RESOLVED
Resolution|--- |FIXED
--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
I have the kludge version working for all add-like ops, I also finished adding
addex to the simulator as part of fixing CA/OV outputs.
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=7b9a2e4eb5d890a067de2f66eaba81f225fd0e1c;hp=17f19a80183d260238e2cf4ba9b78ccac9fe5807
commit 7b9a2e4eb5d890a067de2f66eaba81f225fd0e1c
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Thu Mar 30 00:55:20 2023 -0700
fix add-like CA/OV outputs
this is a massive kludge, but that's what lkcl requested due to time
constraints
commit f1a4430f6b54872f673375c42bfd301a089df05f
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Thu Mar 30 00:54:22 2023 -0700
fix broken test case
forgot to set the expected value to the input value for inputs that aren't
outputs
commit 158e9113030b59b5391ea996ce7ad906c95ea2fd
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Thu Mar 30 00:02:56 2023 -0700
add addex to simulator
works, except it has incorrect CA/OV outputs, which I'll fix as part of
fixing all add-like ops
commit 168bbcffd49637a20f4f980677de31c83cfdf048
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Mar 29 22:00:43 2023 -0700
fix typo when getting pseudo-code output variables
commit 06c05d4c7cbd27d40a5846d0fb3f91a99e1c5c93
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Mar 29 21:38:02 2023 -0700
switch to testing Rc=1 variants
commit f23c637ead369566feb29c1d94da8af14d300512
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Mar 29 21:30:53 2023 -0700
fix `neg[o].` causing the simulator to raise TypeError
commit cd33210ab1516db05cbbf178db02fe889b6cb4f5
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Mar 29 20:03:43 2023 -0700
add case_nego_
commit 60410f30b66aa056f74bfea5c710ad81e618bf6b
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Mar 29 19:02:19 2023 -0700
rename le -> lt since CR bits are lt, gt, eq, and so, not le
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