[Libre-soc-bugs] [Bug 1027] New: implement "necessary" additions to SVP64 and Scalar Power ISA

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1027

            Bug ID: 1027
           Summary: implement "necessary" additions to SVP64 and Scalar
                    Power ISA
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Milestones
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

In the OPF ISA WG Grant 2022-08-051 there is considerable work to be
done in submitting almost 100 instructions via the OPF's External RFC
Process. Adding to this workload is greatly undesirable however under
certain circumstances may prove necessary, was already planned, or
may be demonstrably greatly beneficial. For example a 2D DCT Mode for
REMAP was planned, as was the design and addition of Integer DCT and
FFT Butterfly instructions. Additionally some 64-bit versions of
SVP64's setvl and REMAP instructions have been planned for some time,
and the CRweird and ternary/binary instructions have to be implemented.

Note that the key difference between this Milestone and the OPF ISA WG
Grant 2022-08-051 is that everything under 2022-08-051 has already been
designed and implemented under the SVP64 ISACaller Simulator. This
Milestone brings the necessary additions up to a point where 2022-08-051
can take over.

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