[Libre-soc-bugs] [Bug 1026] New: implement Draft Instructions in nmigen HDL

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1026

            Bug ID: 1026
           Summary: implement Draft  Instructions in nmigen HDL
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

Unit tests and ISACaller Simulator implementation exists for
the various Draft ISA instructions to be proposed under bug
#52 (NLnet 2022-08-051) but HDL for inclusion in Libre-SOC
Core does not yet exist.  There are approximately 50 new
IEEE754 Transcendental instructions to be added, several
bitmanip instructions, and the BigInt 3-in 2-out (64-bit carry)
instructions.
(TODO: link to the appropriate OPF ISA WG bugs: #NNNN #NNNN)

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