[Libre-soc-bugs] [Bug 1116] evaluate, spec, and implement Vector-Immediates in SVP64 Normal

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1116

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)

>     sv.addi/vi rt,0,#nnnn

NOT to be implemented this way.  see comment #6 which **IS** the
implementation.  the bit that is added to SVSTATE is to be added
similar to the "persistence" bit.  the FOLLOWING INSTRUCTION
and the following instruction ONLY shall have its immediates
extended to a Vector, implicitly. there shall no **NO** changes
to Normal/LDST/CRops Modes.

application of REMAP to Vector-Immediates shall be prohibited at
this time (but allowed as usual on registers used)

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