[Libre-soc-bugs] [Bug 1025] create IEEE754 FP Pipelines and decoder for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1025

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
I adjusted the costs for different tasks, and figured out what would fit in our
EUR 8000 budget (it ended up excluding all Libre-SOC instructions, so I think
some of those should just be moved to #1026 where we explicitly have a budget
for Libre-SOC instructions)

I picked:
* add FPSCR and rounding-mode definitions to ieee754fpu
  already done
* add FPSCR and FP registers and dependency-tracking to soc.git
  needed for everything else
* add PowerISA SINGLE/DOUBLE conversion functions
  needed for nearly everything else
* add FP loads to soc.git
  we need a way to get data in/out of FP registers and loads/stores are what
  compilers currently use (they don't support m[ft]fpr yet)
* add FP stores to soc.git
  same as FP loads reasoning
* FP move/sign-bit-manipulation
  data in registers needs to move around
* FP add/sub
  common and fits in budget
* FP select
  exactly fits in EUR 400 left over from everything else
* FPSCR manipulation
  we need a way to get data in/out of FPSCR

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