[Libre-soc-bugs] [Bug 1033] Implementation and enhancement of "Test API"

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1033

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=a1ba910b1ac26158648b69d5cbd7556d9be3a6ef

important clarification -- afaict this task is adding new `StateRunner`
and `State` subclasses for FPGA/verilator/etc.
This task is *not* for creating a new framework or choosing an existing
framework,
we already have one with implementations for pypowersim, nmigen simulation of
the
libre-soc core, and `ExpectedState`. maybe also QEMU through GDB, icr.

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