[Libre-soc-bugs] [Bug 1135] add FPSCR and Rounding classes to ieee754fpu

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1135

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/main_stage.py;h=8127e2#l364

OP_SC is treated as a non-optional "branch that happens to swap
MSR and PC with SRR0/1".

OP_TRAP *again* would have Shadow-Hold in an OoO core but for
both TestIssuer and SimpleInOrderCore there is flat-out no chance.
stall is the only "safe" option.

now you know why i said "do everything as FSMs" because there *is*
no "high performance" here.  only one FP operation must be allowed
at a time anyway.

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