[Libre-soc-bugs] [Bug 1135] add FPSCR and Rounding classes to ieee754fpu

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1135

--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> XER regfile:
> 
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;
> h=5ef301a8bf
> 
> it should be obvious that a corresponding FPSCR regfile is needed,
> and that the bits in each "register" should be of equal length.

really we only need 1 register for each of the 3 different FPSCR parts, those
parts are not equal length:
volatile part: 7 bits
sticky part: like 10-15 bits
control part: the rest, like 10-20 bits.

though if we add register renaming at some point (I don't think we're planning
on that) we'll need more than 1 of each.

if the pipeline code can only handle 2-bit registers, then it needs
improvement.

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