[Libre-soc-bugs] [Bug 1135] add FPSCR and Rounding classes to ieee754fpu

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1135

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
XER regfile:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;h=5ef301a8bf

it should be obvious that a corresponding FPSCR regfile is needed,
and that the bits in each "register" should be of equal length.
if there are extras then tough luck: see line 215:

    215     SO=0 # this is actually 2-bit but we ignore 1 bit of it

although subdividing (grouping) the reg-bits into chunks ("all the other bits")
sounds reasonable, to be honest if they are "fake" then don't bother, just
hard-code them with a Const in the mv routine: this is done with MSR as
well as XER so it's standard fare.

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