[Libre-soc-bugs] [Bug 1026] implement Draft Instructions in nmigen HDL

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1026

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> (In reply to Jacob Lifshay from comment #9)
> 
> > ah, yeah, that too. I was thinking of sharing pipelines because all of the
> > div/mod/sqrt stuff has similar hardware that can be shared.
> 
> yes. needs planning. and diagrams. shriya has offered last week to do some,
> this would be perfect.

yeah, i'm thinking we use goldschmidt div/sqrt with a final step to do fixup
and/or mod/rem, which gives us all of div, rem, mod, sqrt, and rsqrt plus fp
versions of those.

it would need a wide (a bit >64 bit) mul-add unit or two and the rom tables
(pretty small, on the order of a few hundred bits).

alternatively, if we want a much smaller unit, we'd just need a few add/sub,
but it would be 20-60 cycles instead of ~15.
> 
> > (In reply to Luke Kenneth Casson Leighton from comment #8)
> 
> > sounds good to me, though I think we could squeeze a few insns under this
> > budget:
> > 
> > * post-update load/stores
> > * set[n]bc[r]
> > * [f]minmax*
> > * fp/int moves
> > * bigint shift ops

we can adjust the list somewhat as we go, since those may be simpler or more
complex than fits in the eur 8000 budget.
> > 
> > all of those should be pretty simple new hw or simple extensions of existing
> > hw
> 
> agreed, and no need to adjust this budget - fit within available.
> ok i think we're probably done on this one?

sounds good!

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