[Libre-soc-bugs] [Bug 947] support insndb-based assembly

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=947

--- Comment #2 from Dmitry Selyutin <ghostmansd at gmail.com> ---
We're moving towards cool assembly and disassembly! Word instructions are
(mostly?) complete; and SVP64 instructions are on the way. I started with
operands, since I still remember how they work and I'd really like to complete
them until I forget it. Then I'll address opmodes.

There are too many changes to recall, but these are major ones:
1. We now support GPR and FPR remap on insndb level, including vectors. There
must be more checks, like checks for ranges, but anyway.
2. We now support a cool and sweet CR operands assembly syntax, in any of these
forms: CR, N*CR, CR*N, BIT+CR, CR+BIT, BIT+N*CR, N*CR+BIT, etc. Again, the
strict checks are to be added later.
3. Disassembly now supports that syntax too, including our home-grown
"<CR>.<COND>" syntax.


An example is below. Be sure to use the latest binutils, since I fixed some
issues in the scope of this task.


$ cat /tmp/test.s && INSNDB=true SILENCELOG=true pysvp64asm /tmp/test.s
/tmp/py.s && echo "### PYSVP64ASM ###" && cat /tmp/py.s && echo "### BINUTILS
###" && powerpc64le-linux-gnu-as -mlibresoc /tmp/py.s -o /tmp/test.o &&
powerpc64le-linux-gnu-objcopy -Obinary /tmp/test.o /tmp/bin.o &&
powerpc64le-linux-gnu-objdump -dr -Mlibresoc /tmp/test.o && echo "###
PYSVP64DIS ###" && time pysvp64dis /tmp/bin.o

sv.isel 2,3,4,28
sv.isel r2,r3,r4,4*cr7+lt
sv.cmpi 5,1,3,2
sv.add *122,56,*3
### PYSVP64ASM ###
.long 0x05400000; .long 0x7C43271E; # sv.isel 2,3,4,28 # sv.isel 2,3,4,28
.long 0x05400000; .long 0x7C43271E; # sv.isel r2,r3,r4,4*cr7+lt # sv.isel
r2,r3,r4,4*cr7+lt
.long 0x05400000; .long 0x2EA30002; # sv.cmpi 5,1,3,2 # sv.cmpi 5,1,3,2
.long 0x054031E0; .long 0x7FD80214; # sv.add *122,56,*3 # sv.add *122,56,*3
### BINUTILS ###

/tmp/test.o:     file format elf64-powerpcle


Disassembly of section .text:

0000000000000000 <.text>:
   0:   00 00 40 05     sv.isel r2,r3,r4,cr7.lt
   4:   1e 27 43 7c 
   8:   00 00 40 05     sv.isel r2,r3,r4,cr7.lt
   c:   1e 27 43 7c 
  10:   00 00 40 05     sv.cmpdi cr5,r3,2
  14:   02 00 a3 2e 
  18:   e0 31 40 05     sv.add  *r122,r56,*r3
  1c:   14 02 d8 7f 
### PYSVP64DIS ###
00 00 40 05    sv.isel r2,r3,r4,cr7.lt
1e 27 43 7c    
00 00 40 05    sv.isel r2,r3,r4,cr7.lt
1e 27 43 7c    
00 00 40 05    sv.cmpi cr1.gt,1,r3,2
02 00 a3 2e    
e0 31 40 05    sv.add *r122,r56,*r3
14 02 d8 7f

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