[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #7)
> You would think, and call it a quirk, R0 is usually handled differently. 
> That's why in a lot of tests you see registers 3,2,1.
> 
> If you look at the psuedo code in PowerISA manual, you'll see
>   if RA = 0 then RT <-EXTS(SI || 16 0)
>     else RT <- (RA) + EXTS(SI || 16 0)
> 
> So basically when RA is 0 its value is ignored and the result is only
> shifted.

from section 1.3.2 page 4 of Power ISA 3.0 Book I:

 (RA|0) means the contents of register RA if the RA
 field has the value 1-31, or the value 0 if the RA
 field is 0.

so, from the pseudocode at this line:

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/fixedarith.mdwn;h=46f635294a0ecda189782a11ae985d443a674578;hb=4495f61303afca9790a9e2c3bab4cf8977c7de11#l27

  19 # Add Immediate Shifted
  20 
  21 D-Form
  22 
  23 * addis RT,RA,SI
  24 
  25 Pseudo-code:
  26 
  27     RT <- (RA|0) + EXTS(SI || [0]*16)

that "(RA|0)" is equivalent to what kyle wrote.

sometimes, bizarrely, you see this:

   if RA = 0 then
     b <- 0 
   else
     b <- (RA)

which i have no idea why the pseudocode writers did not just use

    b <- (RA|0)

perhaps one day we will be able to contact them and find out

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