[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Oct 23 11:12:11 BST 2021


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to vklr at vkten.in from comment #3)
> Need help for understanding the construct and meaning.
> def case_addis_nonzero_r0_regression(self):
> lst = [f"addis 3, 0, 1"]
> Here 3 means GPR3 register, 0 means GPR0 register and value of SI=1


> initial_regs[0] = 5
> here GPR0 is assigned value 5

so on startup of the simulator, the initial reg 0 will be 5, yes.

> e = ExpectedState(initial_regs, pc=4) ||| What does it do?

this says "we expect the state to be what is in the variable e" 

> e.intregs[3] = 0x10000
> is it here GPR3 is reassigned the value of 0x10000

and ExpectedState took a *copy* of its input GPR table,
which was "e.intregs[0] = 5" already (GPR0=5), now GPR3 is modified
to 0x10000

so, on completion of the execution of "addis GPR3 GPR0 1",
we EXPECT that GPR0 is still 5,
we EXPECT that GPR3 is 0x10000,
we EXPECT that pc=4.

> self.add_case(Program(lst, bigendian), initial_regs, expected=e) ||| what
> this does?

it says, "please add a case (add_case) of a Program to be run
(here is the assembly listing, lst), with the initial regs,
and when completed we EXPECT the results to be as we defined
in the variable e"

it is like reading English, but with some words missing.

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