[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 21 16:58:47 BST 2021


--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
wow.  just... wow.  it actually frickin worked.  thiis was all it took
(after having the "hack" set is_lhs).

+++ b/src/ieee754/part_cat/cat.py
@@ -120,7 +122,10 @@ class PartitionedCat(Elaboratable):
                 with m.Case(pbit):
                     # direct access to the underlying Signal
-                    comb += self.output.sig.eq(Cat(*output))
+                    if self.is_lhs:
+                        comb += Cat(*output).eq(self.output.sig) # LHS mode
+                    else:
+                        comb += self.output.sig.eq(Cat(*output)) # RHS mode

         print ("PartitionedCat end")
         return m

commit bc4f03efdc4ae932f2650bec0807070398178aa6 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Thu Oct 21 16:56:51 2021 +0100

    add LHS support into PartitionedCat. amazingly - stunningly - it works


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