[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 21 03:50:33 BST 2021


--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)

> i do not believe it necessary to do "full AST walk" of the AST looking
> for things like:
>     comb += Cat(Cat(a, b), c, z[3:5]).eq(d)

more to the point: attempts to do exactly that will result in
calls inside ast.py attempting to perform Value.cast() on objects
that do not derive from Value/UserValue.

unless the temporary classes do in fact do exactly that, in which
case there is not much point having them: the existing submodules
might as well just be created.

however... the tricky bit there is making sure that the missing
information (LHS or RHS) is propagated to the submodule *BEFORE*
the submodule's elaborate() function is called.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list