[Libre-soc-bugs] [Bug 731] potential design oversight in Partitioned SimdSignal Cat/Assign/etc lhs/rhs

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Oct 17 22:49:45 BST 2021


--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)
> submodule designs for PartitionedCat, PartitionedRepl, PartitionedAssign
> etc. which may only cope at present with the AST Construct being on
> the rhs:

We won't have to worry about Repl, since nmigen only supports assigning to
Signals and Slice, Cat, and Part:

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