[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 14 10:04:49 BST 2021


--- Comment #109 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #108)

> yeah, I can do that tomorrow (actually today, but you get what I meant).


the blanking mask is important to allow submodules
to not allocate unnecessary gates.


* with the width(s) now being the vector element width, intermediary
  scalar computations "mb = Signal(6)" for e.g. rlwinm will now
  be straight-SIMDified without any other code changes other than

   with ctx:
      mb = ctx.SignalKls(6) # 6=> lane_shapes => {0:6,1:6,2:6,3:6}

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