[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #70 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #60)

thinking about it again, maybe we need to have a scoped global dict of
supported partitioning modes (which elwidths to use for which lanes):
example for FP:
simd_modes = {
    # 4 lanes each with the shape for F16
    SimdMode.F16x4: (FpElWid.F16,) * 4,
    # 4 lanes each with the shape for BF16
    SimdMode.BF16x4: (FpElWid.BF16,) * 4,
    # 2 lanes each with the shape for F32
    SimdMode.F32x2: (FpElWid.F32,) * 2,
    # 1 lane with the shape for F64
    SimdMode.F64x1: (FpElWid.F32,),
    # we can add other combinations later, such as:
    #SimdMode.F16x2_F32x1: (FpElWid.F16,) * 2 + (FpElWid.F32,),
    # or even int/fp combinations:
    #SimdMode.I32x1_F32x1: (IntElWid.I32, FpElWid.F32,),
}

(By this point, ElWid would only be used by the SimdSignal system as a lane
kind designator, so maybe we should have a separate LaneKind enum type and not
use ElWid here, ElWid could still be used for the elwid Signal, of course)

For an ALU:
simd_mode = Signal(SimdMode)
# simd_mode replaces elwid as the Signal that determines which
# lanes are enabled...it can be set based on elwid of course.

so, if we have the current value of simd_mode == SimdMode.F16x2_F32x1, then:
s = SimdSignal(XLEN)
# s has lanes with shapes u16, u16, and u32.

mantissa_field = SimdSignal({
    ElWid.F16: 10,
    ElWid.BF16: 7,
    ElWid.F32: 23,
    ElWid.F64: 52,
})
# mantissa_field has lanes of u10, u10, and u23

unbiased_exponent = SimdSignal({
    ElWid.F16: signed(5),
    ElWid.BF16: signed(8),
    ElWid.F32: signed(8),
    ElWid.F64: signed(11),
})
# exponent has lanes of s5, s5, and s8

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