[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Oct 11 14:42:56 BST 2021


--- Comment #67 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ah! i realised a couple of things:

1) setting a fixed width needs to be *optional* not
   mandatory.  we need *both* the option to specify
   that the width is to be per *element* (lane) as
   a fixed quantity *and* the option to set the overall

2) and another option to say that based on the fixed
   width and based on the partition counts the element
   widths should be automatically calculated

def layout(elwid, part_counts, lane_shapes=None,
    if lane_shapes is None:
        lane_shapes = {}
        for p, c in part_counts.items():
           # calculate width of each partition
           lane_shapes[p] = lane_width // c
    if not isinstance(lane_shapes, Mapping):
        lane_shapes = {i: lane_shapes for i in part_counts}

of course an assert if both lane_shapes and fixed_width
are None.

basically, the actual registers are 64 bit so we *have* to
have a way to declare explicit subdivisions of exactly 64 bit.
but, for intermediary signals you want to say (such as for shift)
with absolute certainty that what you are using to shift is
a fixed width for all elwidths.

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