[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #53 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #51)

> I think copying the existing PartitionedSignal and naming the copy
> ElwidthSimdSignal is better than having it be a subclass...subclassing will
> make a bunch of messy unnecessary interactions.

it's surprisingly small (and regular), needing only 3 functions/properties

https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_repl/repl.py;h=364b7721c9ec896e9e5d0cbf133404f3631ad059;hb=HEAD#l90

1) the thing to switch on (line 90)
2) the list of values to create cases from
3) (as an optimisation) a mask identifying padding-only lanes,
   stopping partial computations in padding lanes from taking
   place.

note 1 and 2 are *not* PartitionedSignal.__Switch__ they are
actual (scalar) Module m.Switch m.Case.

lines 90-92 in repl.py would become something like:

   with m.Switch(self.something.get_selector()):
       for pbit in self.something.get_allowed_cases():   

that is *literally* the extent of the modifications required
to allow PartitionedSignal submodules/subfunctions to adapt.

> Also, naming it Simd is waay
> shorter than Partitioned.

yeah i'll do a (big) rename in the morning. SimdSignal?

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