[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #43 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #40)
> (In reply to Jacob Lifshay from comment #36)
>  
> > only if you never run `opt`...expression deduplication is a pretty trivial
> > compiler optimization. In my experience, yosys deduplicates built-in
> > expressions just fine.
> 
> not on TestIssuer or other complex desigbs it doesn't

hmm, it probably only works within each module, not across modules.

> 
> > > 
> > > it was the submodules.
> > 
> > we can deduplicate expressions ourselves pretty easily:
> 
> ooo niiiice, that's really valuable and exciting.
> 
> i bet a similar trick would be possible to deploy for autocreating
> intermediary temporary Signals.
> 
> can you drop this into nmutil?

sure! Python's GC just had a heart-attack at the sight of it, but oh well. Good
thing we don't have long-running programs that need PartitionedSignal.
> 
> > > the next problem is: how do you now reduce the number of Case() statements
> > > needed to four, or, more to the point, on doing so which bits of data do
> > > you copy from which partition, without the prerequisite information?
> > 
> > easy,
> 
> it was a rhetorical-ish question as part of the reasoning chain, but hey :)
> let's go through it.
> 
> > each `part_wid` wide bit slice in any PartitionedSignal can be
> > independently muxed -- as long as the condition is first converted to the
> > layout:
> > {
> >     ElWid.I8: 1,
> >     ElWid.I16: 1,
> >     ElWid.I32: 1,
> >     ElWid.I64: 1,
> > }
> > with padding being a sign-extended version of each lane... Aka. the result
> > of PartitionedSignal.bool(). (or what *should* be the result if design were
> > left to me).
> 
> ah.  ok, so with so much code already having been written, and it taking 5
> months, and you weren't contributing at the time, we have to be pragmatic
> and fit with the existing design (and, it's simply good engineering
> practice to finish something first rather than discard it 90% the
> way to completion)

Luckily, the exact bit layout resulting from bool matches the layout I wanted,
all that needs to happen is to declare all but each lane's lsb as sign-extended
padding bits by replacing the result's layout. no additional gates needed.
> 
> redesigning the entire suite of submodules (12 and counting) to fit elwidth
> is both unrealistic and undesirable, but there *is* a way to retrofit by
> having an adapter - layout() - create the values that the PartPoints
> mask *should* be set to for any given elwidth.

oh, yeah, part_points is another member needed for SimdLayout. oops, forgot
that.

> in this way we do *not* have to discard 5 months of work.
> 
> the example you gave, i apologise i couldn't follow it, it appears
> to be a different design paradigm which is not the focus of the
> discussion.

oh, it is how to handle m.If/Switch/Case with part-wise assignment. it uses the
approach of translating all but the final assignment to just data-flow
ahead-of-time, letting yosys handle the final assignment translation.

> tomorrow i will drop the layout() function into the mix and i think
> i have enough of a handle on things to convert to elwidth.

oh, i can do that...i'll convert PartitionedSignal + unit tests to use
SimdLayout. I'd guess it'll take me the rest of today. I'll be busy all
weekend, so hopefully that won't be too much of a problem...

> however because it would involve a massive duplication of the
> test suite, or a disruptive alteration of the unit tests, i'll do it
> as a separate class that inherits from PartitionedSignal, and
> think about how to go from there

iirc nothing actually uses PartitionedSignal yet, so a API break to using
SimdLayout shouldn't be as big a problem.

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