[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 8 01:42:13 BST 2021


--- Comment #37 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #36)

> # assign e.eq(f)
> rhs = f.cast_to(e.layout)
> for i in range(part_count):
>     with m.If(cond_stack[-1].sig[i]): # cond_stack all have part_wid == 1
>         # slice computation should just be e.layout.part_slice(i)
>         start = e.layout.part_wid * i
>         s = slice(start, start + e.layout.part_wid)
>         m.d.sync += e.sig[s].eq(rhs.sig[s])
> # Elif.exit

This works because, for each lane that is enabled, all parts are assigned due
to all bits in the condition for that lane being identical due to being a
sign-extended bool. padding being assigned along with their corresponding lanes
isn't a problem.

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