[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Oct 7 22:18:56 BST 2021


--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #30)

> there aren't actually any signals there...if there were a signal, it'd be
> like:
> for i in range(4):
>     m = Module()
>     elwid = Signal(2)
>     pp,b,c,d,e = layout(elwid, part_counts, unsigned(3))
>     def process():
>         yield elwid.eq(i)
>         pp = yield from pp.get_values() # get nmigen to evaluate pp
>         pprint((i, (pp,b,c,d,e)))
>     sim = Simulator(m)
>     sim.add_process(process)
>     sim.run()

ah *ha*!  ok.

now i get it.

ok so what i envisaged would be two separate functions (one which allocates
an actual pp mask after determining the length, followed by a *second* one
that would involve a Switch statement on the elwidths, you came up with
an elegant solution that merged the two.

the key function around which that hinges is add_p().



what are the implications of that being a nmigen AST
code-fragment rather than a plain slice on a Signal...
i'll have to think that through.

> the elwid input parameter is a nmigen Value, 

yep, totally got it.  which means if the elwidth is an
Enum it still works, and if it's a 3 bit or 4 bit Signal
it *still* works.

like it.

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