[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #30 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #27)
> (In reply to Jacob Lifshay from comment #23)
> > this is a misunderstanding, which i'm assuming by your later comments you
> > figured out...
> 
> i hadn't.

oh, you still misunderstand...
> 
> > The code creates *one* PartitionPoints based on an input elwidth
> > signal/value.
> 
> the usage for-loop confused me from the examples, when it set that
> elwidth to zero width:
> 
> for i in range(4):
>     pprint((i, layout(i, part_counts, unsigned(3))))
> 
> if i am reading you correctly, that's a zero-width Signal.

there aren't actually any signals there...if there were a signal, it'd be like:
for i in range(4):
    m = Module()
    elwid = Signal(2)
    pp,b,c,d,e = layout(elwid, part_counts, unsigned(3))
    def process():
        yield elwid.eq(i)
        pp = yield from pp.get_values() # get nmigen to evaluate pp
        pprint((i, (pp,b,c,d,e)))
    sim = Simulator(m)
    sim.add_process(process)
    sim.run()

the elwid input parameter is a nmigen Value, not a Shape. This is what type
annotations would have told you...though it does also need docs...i got it to
work right before our meeting and ran out of time.

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