[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=713

--- Comment #10 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #9)
> going back to what is needed:
> 
> * elwidth as input
>    (or, an enum, or string)
> * for each elwidth, an actual width (power of 2)
>    (or, the number of subdivision)
> * and a (nonp2) "use this many bits" width
> 
> this suggests a dict as the spec.  mantissa:
> 
> { 0b00 : (64, 53),  # FP64
>   0b01 : (32, 23),  # FP32x2
>   0b10 : (16, 10),  # FP16
>   0b11 : (16, 5),  # BF16
> }
> 
> no types, no classes.

Oh, what I have as types that can be SimdLayout.cast (like nmigen Shape.cast)
are 1 of 3 options:
1. dict-like types that map lane-size-in-abstract-parts to Shape-castable
values:
This (after Shape.cast-ing all dict values) is the canonical internal
representation of a layout (stored in self.lane_shapes).
example:
{ # keys are always powers of 2
    1: 5, # 1-part lanes are u5
    2: unsigned(3), # 2-part lanes are u3
    4: range(3, 25), # 4-part lanes are u5 since that fits 24
    8: MyEnum, # 8-part lanes are u10, assuming MyEnum fits in u10
}
or:
{ # keys are always powers of 2
    1: signed(1), # 1-part lanes are i1
    2: signed(3), # 2-part lanes are i3
    4: range(-30, 25), # 4-part lanes are i6 since that fits -30
    8: MySignedBoolEnum, # 8-part lanes are i1
    16: signed(0), # 16-part lanes are i0, zero-bit shapes are supported
}

2. callables that take lane-size-in-abstract-parts and return Shape-castable
values. Useful for making non-uniform layouts quickly.
example:
lambda lane_size: signed(lane_size * 8)

dict equivalent (for part_count == 8):
{
    1: signed(8),
    2: signed(16),
    4: signed(32),
    8: signed(64),
}

3. a Shape-castable value that is used for all lane-sizes. Useful for making
uniform layouts quickly.
example:
5

dict equivalent (for part_count == 8):
{
    1: unsigned(5),
    2: unsigned(5),
    4: unsigned(5),
    8: unsigned(5),
}


>From that dict-equivalent (stored as self.lane_shapes), it computes the minimum
number of bits needed for each abstract part required to pack those chosen lane
shapes into their abstract parts -- the bits needed per abstract part is
self.padded_bits_per_part (same value for all parts).

>From that, member functions can calculate the total required signal width in
bits (self.width), and the unpadded/padded slices for each lane
(self.lane_bits_slice(lane, include_padding=False/True)).

> 
> turning that into PartitionPoints, a simple
> function creates a dict and a mask Signal.

PartitionPoints needs to be re-vamped to carry all the necessary information --
that's what SimdLayout is. The mask signal is wrapped by SimdPartMode, which
provides all the necessary introspection and utility functions to make it easy
to use.

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