[Libre-soc-bugs] [Bug 713] PartitionedSignal enhancement to add partition-context-aware lengths

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Oct 1 00:24:40 BST 2021


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i gave this some thought and i believe it should be reasonably
straightforward to adapt PartitionedSignal and the 15 or so
specialist modules behind it to cope with adaptive Signal truncation.

the more recent ones (Cat, Assign) should be easy to enhance
because they loop through all combinations available to the
mask and create a switch statement.

truncating and zeroing the output from each lane, in each
of those switch statements, is therefore pretty straightforward:
it can be handled by a function which performs the truncation.

the earlier ones (eq gt le shift) which have already been optimised
and are based around a gate-level design principle will take a bit
more thought and effort.

based on appx average:

* half a day per code-change (to add to the specialised module)
* half a day for unit test
* half a day for Formal Proof

and there being around 20 Type I (Ast) "operators":

* shift add sub neg
* or not and xor
* eq gt lt
* Assign Cat Part Switch Repl
* bool all some any xor

the time estimated for this task is around 35 days.  some of these will
be less (and, or, not), some a lot longer (shift/rot) due to them
slready being optimised, and particularly complex (3 weeks) to originally

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