[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #56 from vklr at vkten.in <vklr at vkten.in> ---
(In reply to Luke Kenneth Casson Leighton from comment #55)
>  240             if imm < 0:
>  241                 e.intregs[3] = (imm + 2**48)<<16
>  242             else:
>  243                 e.intregs[3] = imm << 16
> 
> can i believe be just:
> 
>                  e.intregs[3] = (imm << 16) & ((1<<64)-1)
> 
> although this may need checking.  again, this relies on
> -ve numbers becoming +ve when &ed.
> 
> -1 & 0b11 ==> 0b11 (i.e. not -0b11)

Corrected the add-equal operator bug as per comment 54.

Yes using bitwise & op makes neg operand +ve, checked it in python3 prompt. So
shortened the code as you put here. And it passed the tests.

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