[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to vklr at vkten.in from comment #46)
> Added expected state to case_extsb
> 
> It does not needed CA or CA32 bit.

yes that sounds right.  in the PDF spec you see "flags" for
each instruction: there is no "extsbo" - no OE=1 - and
this is because carry and carry32 are meaningless for extsb.

> In case_0_adde_expected I could not permute and combinate the possible
> outcomes.
> I think only those who know the OPENPOWER architecture can find out!

case_0_adde_extended is a copy of case_0_adde...

(In reply to vklr at vkten.in from comment #47)

> I successfully worked out case_0_adde and added the expected state!

... which you managed to do here, hooray!

-- 
You are receiving this mail because:
You are on the CC list for the bug.