[Libre-soc-bugs] [Bug 748] NLnet toplevel Milestone 2021-08-049 coriolis2

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Nov 23 12:44:12 GMT 2021


--- Comment #3 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC
> to discuss milestones.  best to have some outline before then!


1. The full scale thing is based upon the hypothesis that we will be able
   to hire our internship. Looked interested, but still.

2. Do not want to make a transistor level LVS for gates. Just read
   correctly the pin order, so we don't have to use a "wrapper"

3. Need to be more clear about the concept of "porting" HiTas/Yagle.
   No real development work involved here. Just updating the licenses,
   migrating to CMake and just a minimum of code cleanup/upgrade
   to compile on recent systems (even that *may* takes time).

4. LEQ: Do we include the "resynthesis case" ? (way more complex, because
   we need to manage booleans equations).

5. GUI frontend now works at a bearable speed, even if it still may be
   improved (remove the complex double buffering maybe).

6. Efabless : if it's about the support of the harness, will do it
   anyway, and quickly (for ChipFlow/Staf and general use).

7. Protection againts hold violations (basic buffer insertion).

8. Mutliple clocks domains, localized clock tree : NGI pointer.

9. Separation between what the internship will do and I will do not 
   clear at this stage. But, in all case the money must go the intern.

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