[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #37 from vklr at vkten.in <vklr at vkten.in> ---
(In reply to vklr at vkten.in from comment #36)
> There is probably a typing mistake (creating a bug) in:
> 
> def case_cmplw_microwatt_1(self):
>    lst = ["cmpl 1, 0, 22, 4"]
> 
> Perhaps it should have been:
>    lst = ["cmplw 1, 0, 22, 4"]
> 
> Please verify and let me know!

Just read manual again (I missed previously) which says:

cmplw cr3,Rx,Ry
eqv to
cmpl 3,0,Rx,Ry

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