[Libre-soc-bugs] [Bug 745] OP_TERNARY instruction

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=745

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #12)
> WIP:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=309b35ee91f1ad6448379a1d804c304dd9681396

i forgot, an additional TODO (now added): basically the contents
of this patch should be shifted to SVP64Asm (as a 32bit instruction)
there are about 6-10 instructions now in that class, and the lst
argument can be chucked at it and it will create a .long xxxxxxxxxx
with the right "stuff".

> https://git.libre-soc.org/?p=soc.git;a=commit;
> h=e281a933b5e0b7b0c85040116a404873f4ee0f17

mm... a case could be made either way for the benefits of having
a separate pipeline vs putting ops into ones with identical
profiles.

basically, instructions must be grouped by their register profile,
*not* by the name of the PDF Page Section in the ISA Manual.

and OP_TERNLOG is an identical register profile to shiftrot.

when more instructions are added, this will start to make sense.
e.g. adding the CR-based variant of OP_TERNLOG, are another
three regs to be added to regspec?

that would make SIX input regs and two output regs!

RA RB RC BA BB BC

this would be quite insane to have a pipeline and a Dependency
Matrix Row with EIGHT registers!

see now why things have to be grouped with other instructions
with a similar register profile?

it is to keep the Dependency Hazard Tracking down to sane levels.

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