[Libre-soc-bugs] [Bug 745] OP_TERNARY instruction

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Nov 17 18:33:49 GMT 2021


--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)
> (In reply to Jacob Lifshay from comment #7)
> > the benefit of using x86's name is someone who has seen the x86 instruction
> > before will know exactly what it does, without having to look it up. The
> > other names are worse cuz they don't indicate that the operation is
> > bitwise... the log in ternlog indicates bitwise logic.
> yep, like it.  ternlog (and ternlogi) it is

k, i'll rename it to ternlog in both the openpower-isa.git and the wiki. imho
the TI-form and TI-field should probably be renamed to TLI.

> if pmux did not exist, or was not covered in nmigen by Array(),
> or if there was some massive inefficiency expected by yosys to
> completely fail to create an optimal binary-fan-out mux-tree,
> then it would be a good idea.

yup, I'll replace it with using Array as suggested. Repl is only needed for the
BitwiseMux-tree version.

> > -- the Repl is to splat each lut bit into an
> > output-width wide value so the BitwiseMux tree has all the right input bits.
> that can be covered by specifying a fixed width as an integer argument
> for both input and output.

umm, the input/outputs are already fixed-width with the width as an integer
argument passed into __init__, i think you've misunderstood how Repl was used

> forcing the API to deal with a case that may - or may not - be even needed
> introduces API and design complexity.

it was needed to convert from each single-bit slice of lut into the width-wide
inputs of the BitwiseMux tree, cuz otherwise you'd end up just assigning the
(cuz slices are unsigned) and only the lsb of the output would be correct, the
rest of the output bits would always be zeros.

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