[Libre-soc-bugs] [Bug 50] nmigen pinmux

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=50

--- Comment #28 from andrey at technepisteme.xyz ---
(In reply to Luke Kenneth Casson Leighton from comment #27)
> https://git.libre-soc.org/?p=pinmux.git;a=commitdiff;
> h=b65a08d04f740bb04db2f4e06728efd1281ff4ec
> 
> Andrey i have to say, "very much good luck working this out" :)
> 
> there are 4 things: they have to be wired together.  i have
> no idea which it is, or which direction: that's down to you
> to work out.  i am partially-dsylexic when it comes to these
> things.  it could be:
> 
> comb += pin.i.eq(io.core.i)
> comb += io.pad.i.eq(self._invert_if(invert, port))
> 
> it could be like that, it could be completely the other way round.
> 
> the 4 things needing connecting are:
> 
> * self._invert_if(invert, port)
> * pin.i
> * io.pad.i
> * io.core.i
> 
> the existing code is:
> 
>     comb += pin.i.eq(self._invert_if(invert, port))
> 
> so that already tells you that it is going to be:
> 
>        comb += pin.i.eq(SOMETHING1)
> and:
>        comb += SOMETHING2.eq(self._invert_if(invert, port)
> 
Before looking into muxes, I tried the following in get_input:
"""
m=Module()
print ("    get_input", pin, "port", port, port.layout)
if pin.name not in ['clk_0', 'rst_0']: # sigh
    (res, pin, port, attrs) = self.padlookup[pin.name]
    io = self.jtag.ios[pin.name]
    m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
    m.d.comb += pin.i.eq(io.pad.i)
    m.d.comb += io.core.i.eq(pin.i)
else: # simple pass-through from port to pin
    print("No JTAG chain in-between")
    m.d.comb += pin.i.eq(self._invert_if(invert, port))
"""
The execution processed all the pins, but I get an AssertionError:
Traceback (most recent call last):
  File "testing_stage1.py", line 319, in <module>
    p.build(top)
  File "/home/rohdo/work/nmigen/nmigen/build/plat.py", line 95, in build
    plan = self.prepare(elaboratable, name, **kwargs)
  File "/home/rohdo/work/nmigen/nmigen/build/plat.py", line 166, in prepare
    fragment._propagate_ports(ports=self.iter_ports(),
all_undef_as_ports=False)
  File "/home/rohdo/work/nmigen/nmigen/hdl/ir.py", line 460, in
_propagate_ports
    self._prepare_use_def_graph(parent, level, uses, defs, ios, self)
  File "/home/rohdo/work/nmigen/nmigen/hdl/ir.py", line 434, in
_prepare_use_def_graph
    subfrag._prepare_use_def_graph(parent, level, uses, defs, ios, top)
  File "/home/rohdo/work/nmigen/nmigen/hdl/ir.py", line 407, in
_prepare_use_def_graph
    add_defs(stmt._lhs_signals())
  File "/home/rohdo/work/nmigen/nmigen/hdl/ir.py", line 394, in add_defs
    assert defs[sig] is self
AssertionError

I looked into that file, but don't really understand, I guess it complains
about an identical name?

> this took 5 months for me to get completely wrong, but that was
> because of litex.  hopefully with nmigen you will get "driver
> conflict errors" immediately if you get it wrong the first time,
> because, here, line 587, the wrong thing will conflict with this
> 
> https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/tap.py;
> h=1f3d424cbd7451c0434e0c71168f5aa0935af860;
> hb=c2bf4810f9f91ced7fcda777b92b86ab353da288#l587
> 
>  586             if conn._iotype == IOType.In:
>  587                 m.d.comb += conn.core.i.eq(Mux(bd2core, io_bd[idx],
> conn.pad.i))
What signals do I need to use to control the Mux itself?
I need a way to select between pad and jtag boundary scan (or am I
over-thinking?)

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