[Libre-soc-bugs] [Bug 739] NGI POINTER Gigabit Router Pinout Considerations

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=739

--- Comment #13 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> jean-paul, one thing: when we discussed the additional clocks
> coming from peripherals (JTAG TCK, RGMII CLK, ULPI CLK) these are inputs
> that are planned to be routed through JTAG Boundary Scan, just like all
> others.
> 
> later (in a future version) they may also be routed through
> pinmux (4 peripherals MUXed
> to/from the exact same IOpad, under GPIO control)
> 
> is that okay?

  I've loosely followed this discussion up until now, I'm not sure
  to follow exactly what the question is. Are there specific
  routing constraints to manage? If so, could you draw a schematic
  or a figure of the layout you expect ?

  Best,

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