[Libre-soc-bugs] [Bug 200] IEEE754 FPU Coriolis2 layout

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Nov 11 14:30:26 GMT 2021


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
                 CC|                            |Jean-Paul.Chaput at lip6.fr
         Resolution|---                         |FIXED
       The table of|                            |lkcl=750
  payments (in EUR)|                            |lip6=6250
     for this task;|                            |
        TOML format|                            |
             Status|CONFIRMED                   |RESOLVED

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

Jean-Paul this was at least successful and showed that a large layout
would be possible.  we also did the Dependency Matrices:

and also i recall we did a manual explicit positioning of large cells,
at the top level, to see how that went, with internal positioning done
in the large sub-cells.

i think we can close this one.

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