[Libre-soc-bugs] [Bug 743] New: TestIssuer does not terminate in svp64 mode test_issuer_svp64.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=743

            Bug ID: 743
           Summary: TestIssuer does not terminate in svp64 mode
                    test_issuer_svp64.py
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

in commit f25faf58a3ed81 the test runner was converted to a new API
which, instead of running single-step concurrently HDL-Simulator instruction 1,
HDL-Simulator instruction 2, .... it is now HDL instruction 1, HDL instruction
2
... followed separately by Simulator instruction 1, Simulator instruction 2 ...

HDL in SVP64 is not correctly detecting a terminating condition, instead
entering a permanent loop.  test_runner.py:

            terminated = yield self.issuer.dbg.terminated_o

this is never being set (in svp64 mode) and therefore the HDL simulation
never terminates.

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