[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 45d50392c8fd4a70867ef82db0bc2f366b408cee (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Nov 7 15:40:17 2021 +0000

    add hazard vectors to Regfiles
    the reason for adding it to Regfiles is because both In-Order and OoO
    need global hazard vectors.

    in the case of In-Order the hazard vector bits are set directly by the
    Issue Engine.

    in the case of Out-of-Order the vector bits are set by way of an
    amalgamation (Great Big Or Gate) of the columns from the DMs

    in either case the vectors are needed, so might as well be added to
Regfiles

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