[Libre-soc-bugs] [Bug 620] New: post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

            Bug ID: 620
           Summary: post-layout simulation needed using cocotb
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Hardware Layout
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

taking the VST (VHDL) files from coriolis2 post-layout modifications
(including insertion of buffers) needs to be verified.  this to be done
using cocotb to connect up to JTAG (c4m-jtag) and perform tests.

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