[Libre-soc-bugs] [Bug 617] add SVP64 predication to TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=617

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)

> so the first phase is to add src-step and dst-step "skipping", based
> on which bits of the predicate mask(s) are zero

this bit is fairly easy and involves TestIssuer FSM only.

> the second phase adds in src_zeroing / dest_zeroing which does NOT
> skip the computation but instead feeds **ZEROs** into either the
> input or the output

this one is very intrusive into the Core class because it stops read and write
of registers.

in ISACaller it is relatively straightforward to do this, but hooking into Core
connections to the regfiles requires masking and telling the CompUnits they do
not need to read/write regfiles.

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